As high precision measurements, parity violating asymmetry experiments require high statistics. To achieve the designed statistical uncertainties, the event rate could be a few hundred kHz up to a hundred GHz. For these ultra high rate parity violating asymmetry measurements, an integrating data acquisition (DAQ) system or scaler-based DAQ is usually used during the main physics measurement, which avoids the necessity for detailed signal information from the detectors. The counting DAQ system, which records all the detailed detector signals, is only used for determining the kinematics, acceptance, and validating background modeling with a low beam current applied. In recent years, with the development of FPGA based modules at Jefferson Lab, using a counting DAQ to read out the detector signals with negligible dead time at a few hundred kHz is achievable, therefore it can be used for the main asymmetry measurement. This is crucial for parity violating asymmetry measurement in deep inelastic scattering (PVDIS) with SoLID to reject the pion background. As part of the SoLID project R\&D, a thorough DAQ testing and optimization is planned, which will help mitigate the risks and costs for the asymmetry experiments. The plans and status of the DAQ R\&D are presented.